In general, the present invention relates to a microcomputer and a semiconductor integrated circuit including an embedded data-transfer device. More particularly, the present invention relates to an effective technology applicable to typically a single-chip data processor or a single-chip microcomputer.
A typical microcomputer comprises functional blocks such as a CPU (central processing circuit) serving as a nucleus component, a ROM (read-only memory) for storing a program, a RAM (random-access memory) for storing data and an input/output circuit for inputting and outputting data which are built on a semiconductor substrate as described on pages 540 to 541 of a publication entitled “LSI Handbook” published by Ohm Corporation on Nov. 30, 1984.
The microcomputer may include an embedded DMAC (direct memory access controller) which is capable of transferring data independently of the CPU. An example of a document describing such a microcomputer is Japanese Patent Laid-open No. Hei 5-307516.
In addition, a microcomputer may have an external-bus-right releasing function for releasing a right to make an access to an external bus to an external device. After the right to make an access to the external bus has been granted to an external device, however, the CPU is still capable of carrying out an operation using an internal bus such as an operation to read out information from the ROM. If a DMAC is connected to the external bus of the microcomputer as an external device, it is possible to transfer data through the external bus using the external DMAC in parallel to an operation based on the internal bus such as an operation to read out information from the ROM. Japanese Patent Laid-open No. Hei 4-24854 is an example of a document describing a microcomputer wherein a CPU's operation based on an internal bus and a DMAC's operation based on an external bus can be carried out concurrently. Japanese Patent Laid-open No. Hei 1-187682 is an example of a document describing the use of 2 DMACs operating concurrently.
The inventor of the present invention studied a microcomputer including an embedded DMAC, a system employing such a microcomputer and a system comprising a microcomputer with a function to grant a right to make an access to an external bus and an external DMAC connected to the external bus.
In the first place, in the case of a microcomputer including an embedded DMAC, the DMAC can be activated by an interrupt request and is capable of operating in modes such as a repeat mode and a block-transfer mode. In a system such as a printer, a microcomputer including an embedded DMAC is suitable for a plurality of processes to control a stepping motor, control of data to be printed on the printer and operations to store incoming data into a memory, allowing a plurality of data-transfer channels to be provided.
Even though the data-transfer control of the DMAC is executed independently of the operation of the CPU, however, data is transferred by the DMAC through a bus shared by the CPU so that bus cycles required for transferring the data inevitably halt the operation of the CPU. Assume for example that data is transferred by an embedded DMAC from a RAM to an input/output circuit. In this case, a data transfer requires 6 states, i. e., 2 states for an access to the RAM, 3 states for an access to the input/output circuit and 1 state for a dead cycle. During these 6 states, the CPU is not capable of using the bus. 1 state is typically but not limited to 1 period of a reference clock signal of a data processing LSI such as a microcomputer.
In a system comprising a microcomputer with a function to grant a right to make an access to an external bus and an external DMAC connected to the external bus, on the other hand, an operation using an internal bus such as an operation carried out by a CPU to read out data from a ROM can be carried out concurrently with an operation carried out by the external DMAC to transfer data through the external bus.
In an operation to grant a right to make an access to the external bus from the microcomputer to an external component such as DMAC, however, the microcomputer must exchange signals such as a request signal and an acknowledge signal with the external component. To be more specific, the microcomputer must recognize a request signal generated by the external component and issue an acknowledge signal to the external component to recognize the request signal, spending an extra time for the exchange of the signals. In addition, in order to avoid a bus-usage collision between the microcomputer and the external DMAC, it is necessary to set a time during which both the microcomputer and the external DMAC are not using the shared bus. Such a time most likely becomes an overhead which has nothing to do with the actual operation to transfer data through the shared bus. When an overhead is required before and after each transfer of data, the overheads have a magnitude which is hardly negligible in comparison with the data transfer period itself. Moreover, if a general-purpose external DMAC is employed, some functions of the DMAC are not utilized. Thus, such a DMAC can not be said to be a cost-effective solution. If a DMAC suitable for a system is developed individually for each system only because a general-purpose DMAC is not cost effective as described above, however, the development of such a DMAC specialized for a system will incur as much a cost as the development of a new LSI separate from the microcomputer, most likely raising a manufacturing-cost problem.